The Reference Guide contains a list of phrases, acronyms, and their definitions. It is meant to assist the student as a quick reference for those instances during the lecture or reading assignment where an acronym is not defined. Every attempt has been made to collect and define as many acronyms as possible; however, it may not contain all acronyms used in this course offering. We encourage students to create their own list as they go through this course and afterward. Your documents will be a living tool that evolves as semiconductor packaging technology evolves in time.

Acronym	Definition
2D	two dimensions
2.5D	two point five dimensions
3D	three dimensions
5G	5th generation mobile network
AES	Auger electron spectroscopy
AIB	add In board or card
ASIC	application-specific integrated circuit
BER	bit error rate
BGA	ball grid array
BW	bandwidth
C4	controlled collapse chip connect
CABGA	chip array ball grid array
CAGR	compound annual growth rate
CCB	Cu core balls
CCD	charge-coupled device
CMOS	complementary-metal-oxide-semiconductor
CoM	computer on module
CoWoS	chip-on-wafer-on-substrate
CPO	Co-packed optics
CSP	chip-scale package
CTE	coefficient of thermal expansion
CUP	capillary underfill
D2D	die-2-die
DARPA	Defense Advanced Research Projects Agency
daWP	decawatt package
DIP	dual-in-line package
DCA	direct chip attach
DDR	double data rate
DLRM	Deep Learning Recommendation Model
DNN	deep neural network
DPAK	decawatt package
DRAM	dynamic random access memory
DSC	dice-side capacitor
DSMBGA	double-sided molded ball grid array
DSP	digital signal processor package
DUT	device under test
EMIB	embedded multi interconnect bridge
EDS/EDX	energy-dispersive X-ray spectroscopy
ENIG	electroless nickel immersion gold
ESD	electrostatic discharge
eWLB	embedded wafer-level ball grid array
FC	flip-chip (to plastic substrate)
FCBGA	flip-chip ball grid array
FinFET	Fin field-effect transistor
FL	flat lead
FOCoS	fan-out chip on substrate
FOWLP	fan-out wafer-level package
FPGA	field-programmable gate array
FTIR	Fourier transform infrared spectroscopy
GBps	gigabit per second
GFX	graphics
HAST	highly accelerated stress test
HAZ	heat-affected zone
HBM	high bandwidth memory
HDI	high-density interconnect
HI	heterogeneous integration
HIR	HI roadmap
HPC	high-performance computing
HTSL	high-temperature storage life
GMCH	Graphics & Memory Controller Hub
IC	integrated circuit
IEEE	Institute of Electrical and Electronics Engineers
IHS	integrated heat spreader
IL	insertion loss
IMC	intermetallic compounds
IP	input
IQA	incoming quality assurance
I/O	input-output
IO	number of connections
IVR	integrated voltage regulator
k	dielectric constant
KGD	known good die
KGSD	known good stacked die
LGA	large-grid array
LNA	low-noise amplifier
LSC	large-side interconnect
LTCC	low-temperature co-fired ceramic
MCM	multichip module
MCP	multichip package
MEMS	micro-electro-mechanical system
MER	modulation error ratio
MOSFET	metal oxide semiconductor field-effect transistor
MSOP	mini-small outline package
mm	millimeter
nm	nanometer
OSP	organic solderability preservative
OIO	optical interconnect or optical input-output
PCB	printed circuit board
PD	phase delay
PGA	pin grid array
PIP	package in package
PLCC	plastic leaded chip carrier
POP	package-on-package
ppb	parts per billion
ppm	parts per million
PBGA	plastic ball grid array
PCL	process control language
PCLe	PCL express
PQFN	power quad flat no-lead
PQFP	plastic quad flat pack
PS	pitch scaling
PTH	plated through-hole
QFP	quad flat package
RDL	redistribution layer
RF	radio frequency
RNN	recurrent neural networks
SAM	scanning acoustic microscopy
SB	solder ball
SCP	single chip package
SEM	scanning electron microscopy
SEMI	Semiconductors Equipment and Material International
SI	signal integrity
SIB	Si interposer bumps
SIMS	secondary ion mass spectrometry
SIP	system-in-package
SLI	second-level interconnect
SMP	surface-mounted package
SOC	system-on-chip
SOJ	small outline J-leads package
SOP	small outline package
SOIC	small outline integrated circuit
SR	solder resist
SRAM	static random access memory
TAB	tape automated bonding
TCNCP	thermo-compression with non-conductive paste
TEPBGA	thermally enhanced plastic ball grid array
TBps	terabit per second
TDR	time domain reflectometry
Tg	glass transition temperature
THB	temperature-humidity-bias reliability test
THM	through-hole mount
TMCL	temperature cycling reliability test
TMV	through mold via
TOP	transistor outline package
TQFP	thin quad flat package
TSOP	thin small outline package
TSSOP	thin shrink small outline package
TSV	through Si via
TTM	time to market
UCIe™	Universal Chiplet Interconnect Express™
UPI	ultra path interconnect contact CPU to CP
VGG	visual geometry group
WDS or WDX	wavelength-dispersive X-ray spectroscopy
WLP	wafer-level package
WL3D	wafer-level 3D package stacking solutions
WLCSP	wafer-level chip scale package
WLFO	wafer-level fan-out
WLSiP	wafer-level system-in package